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INTRUSION&FIRE ALARM ADDRESSABLE 20-LOOP CONTROL DEVICE
16
“Armed” – the alarm loop is monitored and its resistance is in normal
range.
“Disarmed” - the alarm loop is not monitored.
“Arm delay” – the arming delay has not yet been elapsed.
“Intrusion alarm” – the detector breaking has been fixed.
“Arm Failed” – the alarm loop was broken when arming.
The intrusion alarm loop is considered as broken if its resistance has
been out of 2…6 KOhm range or skipped more then 10% (refer to “10%
Deviation Blocking” parameter). The breaking of the armed loop leads the
loop to the “Intrusion Alarm” status.
The type 4 alarm loop resolving time is 70 ms or 300 ms depending
on “300 ms Integration” parameter value.
The compatibility of loop resistance and the corresponding status can
be shown at the Table 3.
The diagram of connection burglary detector to the type 4 alarm loop
is contained into the Appendix E.
The type 5 is the burglary alarm loop with tamper check.
The alarm loop includes burglary detector with normally closed con-
tacts and tamper detector.
The alarm loop statuses can be:
“Armed” – the alarm loop is monitored and the resistance is in normal
range.
“Disarmed” - the alarm loop is not monitored.
“Arm Delay” – the arming delay has not yet been elapsed.
“Intrusion Alarm” – the detector breaking has been fixed.
“Arm Failed” – the alarm loop was broken when arming.
“Tamper Alarm” – the loop being disarmed, the tamper has actuated.
“Loop Trbl Short” - the loop being disarmed, its resistance is less then
100 Ohm.
When alarm loop is armed then more than 10% hopping, or the de-
tector actuation (opening of its burglary contact), or tamper actuation
switches the loop to the “Intrusion Alarm” mode. When alarm loop is not
armed (being in statuses “Disarmed”, “Arm delay” or “Arm failed”) tamper
actuation switches the loop to the “Tamper Alarm” status. The loop short
failure is the cause of “Loop Trbl Short” status.
The type 5 alarm loop resolving time is 70 ms or 300 ms depending
on “300 ms Integration” parameter value.
The compatibility of loop resistance and the corresponding status can
be shown at the Table 3.
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